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1 standard products ut54actq16374 radhard cmos 16-bit d flip-flop ttl inputs, and three-state outputs datasheet may 16, 2012 www.aeroflex.com/radhard features ? 16 non-inverting d flip-flops with three-state outputs ? guaranteed simultaneously switching noise level and dy- namic threshold performance ? buffered positive edge-triggered clock ? separate control logic for each byte ? guaranteed pin-to-pin output skew ? 0.6 ? m commercial radhard tm cmos - total dose: 100k rad(si) - single event latchup immune - seu onset let >95 mev -cm 2 /mg ? high speed, low power consumption ? output source/sink 24ma ? standard microcircuit drawing 5962-06245 - qml compliant part ? package: - 48-lead flatpack, 25 mil pitch (.390 x .640) description the 16-bit wide ut54actq16374 d flip-flop is built using aeroflex?s commercial radhard tm epitaxial cmos technolo- gy and is ideal for space appli cations. this high-speed, low pow- er ut54actq16374 d flip-flop is designed for bus oriented applications. a buffered clock (cp) and output enable (oe ) are common to each byte and can be s horted together for full 16-bit operation. the ut54actq16374 ar e particularly suitable for implementing buffer registers, i/o ports, bidirectional bus driv- ers and working registers. each fl ip-flop will store the state of their indivdual d inputs (in) that meet the setup and hold re- quirements on the low-to-high clock (cpn) transition. with the output enable (oe n) low, the contents of the flip-flops are avail- able at the output. when oe n is high, the outputs go to high impedance state. operation of oe n input does not affect the state of the d flip-flops. pin description logic symbol pin names description oe n output enable input (active low) cpn clock pulse input i0-i15 inputs o0-o15 outputs (1) oe 1 c1 (47) i0 (46) i1 (44) (2) o0 (5) (3) o1 i2 (43) i3 (41) i4 (40) i5 o2 (9) o5 (8) o4 (6) o3 (38) i6 (37) i7 (12) o7 (11) o6 (24) en4 c3 (48) cp1 en2 (36) i8 o8 (13) (35) i9 (33) i10 (32) i11 (30) i12 (29) i13 (27) i14 (26) i15 (16) o9 o10 (20) o13 (19) o12 (17) o11 (23) o15 (22) o14 (14) oe 2 (25) cp2 oe 1 2 3d 4 1d
2 pinouts 1 2 3 4 5 7 6 48 47 46 45 44 42 43 oe 1 o0 o1 v ss o2 o3 v dd cp1 i0 i1 v ss i2 v dd 8 41 o4 i4 i3 9 40 o5 i5 10 39 v ss v ss 48-lead flatpack top view o6 o7 o8 o9 v ss o10 o11 o12 o13 11 12 13 14 15 17 16 18 19 20 v ss o14 o15 oe 2 21 22 23 24 38 37 36 35 34 32 33 i6 i7 i8 i9 v ss i11 31 v dd i10 30 i12 29 i13 28 v ss 27 i14 26 i15 25 cp2 v dd
3 function table inputs output operation oe n cpn in on h h l z hold h h h z hold h ? l z load h ? h z load l ? l l data available l ? h h data available l h l qo no change in data l h h qo no change in data
4 logic diagram o7 o6 o5 o4 o3 o2 o1 o0 i cp i cp i cp i cp i cp i cp i cp i cp i0 i1 i2 i3 i4 i5 i6 i7 0 0 0 0 0 0 0 0 cp1 oe1 byte 1 (0:7) (48) (48) (1) (2) (3) (5) (6) (8) (9) (11) (12) (8) (47) (46) (44) (43) (40) (38) (37) (41) o8 o9 o10 o11 o12 o13 o14 o15 i cp i cp i cp i cp i cp i cp i cp i cp i15 i14 i12 i11 i10 i9 i8 0 0 0 0 0 0 0 0 cp2 oe2 byte 2 (8:15) i13 (13) (14) (16) (17) (20) (22) (23) (19) (36) (35) (33) (32) (29) (27) (26) (30) (25) (24)
5 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation ex posure within the limits defined in the table. 2. not tested, inherent of cmos technology. absolute maximum ratings 1 note: 1. stresses outside the listed absolute maxi mum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the opera tional sections is not recommend ed. exposure to absolute maxi mum rating conditio ns for extended periods may affect device reliability and performance. recommended operating conditions parameter limit units total dose 1.0e5 rad(si) sel immune >108 mev-cm 2 /mg seu onset let >95 mev-cm 2 /mg neutron fluence 2 1.0e14 n/cm 2 symbol parameter limit (mil only) units v i/o voltage any pin during operation -.3 to v dd +.3 v v dd supply voltage -0.3 to 6.0 v t stg storage temperature range -65 to +150 ? c t j maximum junction temperature +175 ? c ? jc thermal resistance junction to case 20 ? c/w i i dc input current ? 10 ma p d maximum power dissipation 310 mw symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 ? c t inrise t infall maximum input rise or fall time (v in transitioning between v il (max) and v ih (min)) 20 ns
6 dc electrical characteristics 1 ( -55 ? c < t c < +125 ? c) symbol parameter condition min max unit v il low level input voltage 2 v dd from 4.5v to 5.5v 0.8 v v ih high level input voltage 2 v dd from 4.5v to 5.5v 2.0 v i in input leakage current 3 v dd from 4.5v to 5.5v v in = v dd or v ss -1 1 ? a i oz three-state output leakage current v dd from 4.5v to 5.5v v in = v dd or v ss -10 10 ? a i os short-circuit output current 4, 5 v o = v dd or v ss v dd from 4.5v to 5.5v -600 600 ma v ol1 low-level output voltage 5 i ol = 24ma -55c, 25c i ol = 24ma +125c i ol = 100 ? a -55c, 25c, +125c v in = 2v or 0.8v v dd = 4.5v to 5.5v 0.36 0.5 0.2 v v ol2 low-level output voltage 5,6 i ol = 50ma -55c, 25c v in = 2.0v or 0.8v v dd = 5.5v +125c 0.8 1.0 v v oh1 high-level output voltage 5 i oh = -24ma -55c, 25c i oh = -24ma +125c i oh = -100 ? a -55c, 25c, +125c v in = 2v or 0.8v v dd = 4.5v to 5.5v v dd - 0.64 v dd - 0.8 v dd - 0.2 v v oh2 high-level output voltage 5,6 i oh = -50ma -55c, 25c v in = 2.0v or 0.8v v dd = 5.5v +125c v dd -1.1 v dd -1.3 v v ic + positive input clamp voltage for input under test, i in = 18ma v dd = 0.0v 0.4 1.5 v v ic - negative input clamp voltage for input under test, i in = -18ma v dd = open -1.5 -0.4 v
notes: 1. all specifications valid for radiation dose ? 1e5 rad(si) per mil-std-883, method 1019. 2. functional tests are conducted in accordance with mil-std-883 with th e following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within the above specified range, but are guaranteed to v ih (min) and v il (max). 3. not more than one output may be shorted at a time for maximum duration of one second. 4. supplied as a design limit, but not guaranteed or tested. 5. per mil-prf-38535, for current density ? 5.0e5 amps/cm 2 , the maximum product of load cap acitance (per output buffer) times frequency should not exceed 3,765 pf-mhz. 6. transmission driving tests are performed at v dd = 5.5v, only one output loaded at a tim e with a duration not to exceed 2ms. th e test is guaranteed, if not tested, for v in =v ih minimum or v il maximum. 7. guaranteed by characterization. 8. power does not include power contri bution of any cmos output sink current. 9. power dissipation specifi ed per switching output. 10.capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 11. this test is for qualification only. v ss and v dd bounce tests are performed on a non-switching (quiescent) output and are used to measure the magnitude of induced noise caused by other simultaneously switching outputs. the test is performed on a low noise bench test fixture. p total power dissipation 7,6,9 c l = 20pf v dd from 4.5v to 5.5v 0.5 mw/ mhz i ddq standby supply current v dd pre-rad 25 o c -55 o c to +125 o c post-rad 25 o c v in = v dd or v ss v dd = 5.5v oe n = v dd oe n = v dd o e n = v dd 10 160 160 ? a ? i ddq quiescent supply current delta, ttl in- put level for input under test v in = v dd - 2.1v for other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 10 ? = 1mhz @ 0v v dd from 4.5v to 5.5v 15 pf c out output capacitance 10 ? = 1mhz @ 0v v dd from 4.5v to 5.5v 15 pf v olp v olv low level v ss bounce noise 11 v in = 3.0v, v il = 0.0v, t a =+25 o c, v dd = 5.0v 1100 -1300 mv mv v ohp v ohv high level v dd bounce noise 11 see figure "quiet output under test" v oh +1200 v oh -1400 mv mv
8 ac electrical characteristics 1 (v dd = 5v ? 10%, -55 ? c < t c < +125 ? c) notes: 1. all specifications valid for radiation dose ? 1e5 rad(si) per mil-std-883, method 1019. 2. verified by functional testing. 3. output skew is defined as a comparison of any two output transitions high-to-low vs. high-to-low and lo w-to-high vs low-to-h igh. 4. differential skew is defined as a compar ison of any two output tran sitions high-to-low vs. low-to -high and low-to-high vs hi gh-to low. 5. guaranteed by characterization, but not tested. symbol parameter min max unit t plh propagation delay cpn to on 2 10 ns t phl propagation delay cpn to on 2 10 ns t pzl output enable time oe n to on 2 9.0 ns t pzh output enable time oe n to on 2 9.0 ns t plz output disable time oe n to on high impedance 2 9.0 ns t phz output disable time oe n to on high impedance 2 9.0 ns t fmax 2 maximum clock frequency 100 mhz t s setup time high or low in to cpn 1.5 ns t h hold time high or low in from cpn 0.5 ns t w clock pulse, high or low cpn 5.0 ns t skew 3 output-to-output skew 1.25 ns t dskew 3 differential skew between outputs 1.5 ns t dskewpp 3,5 part-to-part output skew between outputs on multiple devices under identical system conditions. 500 ps test load or equivalent 1 v dd 40pf 100 ? v dd 100 ? ? ? notes 1. equivalent test circuit means that dut performance will be co rrelated and remain guaranteed to the applicable test circuit, above, whenever a test platform change necessitates a deviation from the applicable test circuit.
t plz t pzh t pzl t phz oe n 5v output normally low enable disable times 5v output normally high 3.0v 1.5v 0v v dd /2 v dd /2 .8v dd .2v dd v dd/2 +0.2 v dd/2 -0.2 .2v dd + .2v .8v dd - .2v t phl propagation delay cpn output t plh v oh v ol v dd /2 3.0v 1.5v 0v bounce noise active outputs v oh v ol quiet outputs under test v olp v olv v ol v ohp v oh v ohv
setup and hold measurements data input 3.0v 1.5v 0.0v cpn input 3.0v 1.5v 0.0v t s t w t h
package figure 1. 48-lead flatpack note: 1. seal ring is connected to v ss . 2. units are in inches. 3. all exposed metalized areas must be gold plated 10 0 to 225 microinches thick. dyer electroplated nickel undercoating 100 to 350 microinches per mil-prf-38535.
ordering information ut54actq16374: smd lead finish: (notes 1 & 2) (c) = gold (a) = hot solder dip (x) = factory option (gold or solder) case outline: (x) = 48 lead bb fp class designator: (q) = class q (v) = class v device type (01) = 16-bit d flip-flop (4.5v - 5.5v) drawing number: 06245 total dose: (note 3) (r) = 1e5 rad(si) federal stock class designator: no options 5962 r 06245 ** * * * notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3.total dose radiation must be specified when orde ring. qml q not available w ithout radiation hardening.
13 ut54actq16374 ut54 **** ***** * * * lead finish: (notes 1 & 2) (a) = hot solder dip (c) = gold (x) = factory option (gold or solder) screening: (notes 3 & 4) (c) = mil temp (p) = prototype package type: (u) = 48-lead bb fp part number:16374 (16374) = 16-bit d flip-flop i/o type: (actq)= ttl compatible i/o level aeroflex core part number notes: 1. lead finish (a, c, or x) must be specified. 2. if an ?x? is specified when ordering, then the part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3. prototype flow per aeroflex manufacturing flows document. tested at 25 ? c only. lead finish is gold "c" only. radiation neither tested nor guaranteed. 4. military temperature range flow per aeroflex manuf acturing flows document. devices are tested at -55 ? c, room temp, and 125 ? c. radiation neither tested nor guaranteed.
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